Willamette:

The first P4 incarnation, codenamed Willamette, is made in a 0.18u process, and features an 8K L1 data cache, a 12000-micro-op trace cache (described as 12kT in the table below; micro-ops are about 64 bits long, so this takes about 100k of SRAM, but since instructions are expanded by about a factor four in the decoding process it's equivalent to about 20k un-decoded), and 256K of L2 capable of delivering 32 bytes a cycle. The front-side bus is 100MHz QDR, for an equivalent of 400MHz; this allows [for an x86] unprecedented memory bandwidth of 3.2GB per second. Versions with half the L2 cache were used in 2002 for the desktop Celeron chip at 1.8GHz and below; they were not competitive with the Tualatin-based Celerons despite their greater clock speed.

Foster:

Released more than a year after the Willamette, this server chip is a Willamette equipped with a 512k or 1024k on-chip L3 cache, and support for hyper-threading. It supports up to four processors.

Northwood:

This is the 0.13u port of the Pentium 4; apart from higher clock rates, it offers a 512K L2 cache. In June 2002, versions with a 133MHz QDR front-side bus (4.2GB/sec) were introduced. Running significantly cooler than Willamette, this was the chip that brought P4 into the mainstream market and made it a viable competitor to Athlon. Versions with 256k and 128k of L2 cache exist, for the mobile-Celeron and desktop-Celeron (2GHz+) markets respectively.

Northwood HT:

In November 2002, perhaps concerned by the then-imminent launch of the AMD Athlon64, Intel released a version of Northwood with hyper-threading enabled. They also fixed certain performance problems with the P4 core at this stage, in particular L1 cache aliasing which had caused trouble in Prestonia. This chip suffers from very high leakage power (40% of total CPU power at 3GHz). The initial launch was with a 133MHz QDR bus, but in March 2003 the bus speed was increased further to 200MHz QDR (6.4GB/sec). It is believed that Intel will back-fill the hyper-threaded range, down to a 2400MHz model which nonetheless uses the 200MHz QDR bus.

Prestonia:

Sold as "Xeon DP", this is a Northwood core with hyper-threading enabled, and with support for up to two processors in a system.

Gallatin:

Sold as "Xeon MP", this is a Northwood core, with hyper-threading, with an on-die L3 cache of one or two megabytes, and with support for up to four processors in a system.

Prescott:

To appear sometime around the middle of 2003 at speeds of "3GHz or more" (I suspect a launch at 3600, though at least one Intel marketting slide leads you to expect 4200), this is the 90nm version of the Pentium 4; it will have 1MB of L2 cache and 16kb of L1 data, support SSE3 (a rather unexciting set of 13 new instructions), and have "improved hyperthreading" (though still only two processor contexts). The front-side bus will start at 6.4GB/sec (200MHz QDR).

Tejas:

Announced at the Spring 2003 IDF, this is the sequel to Prescott. Probably it's a 90nm chip with a redesigned, extended pipeline; it uses a 775-contact non-pinned socket, and is likely to launch in mid-2004 at around 5GHz, on an 8.3GB/sec or faster bus.

K7:

The first Athlon core was the K7. This used a 200MHz front-side bus, and a separate bus to commodity SRAMs for the level-2 cache; these were packaged in a cartridge physically but not electronically similar to the P2 one.

K75:

In December 1999, AMD started producing Athlon processors made in a 0.18u process; by February 2000, most new Athlons used the K75 core. This isn't just a process shrink of the K7, though about the only programmer-visible modification is that it supports the Deschutes FXSTORE command (possibly in preparation for the K8 64-bit x86 extensions).

Spitfire: Model 3, Duron CPU, 600Mhz to 950Mhz, 200 FSB, 1.6v, 64k L2

This core is to Thunderbird roughly as Cu128 is to Coppermine; it has 64k rather than 256k of full-speed L2 cache, is sold at lower speed grades, and is significantly cheaper. However, it runs withthe full 200MHz bus speed of its larger brother, and outperforms the Cu128 core very substantially.

Thunderbird: Model 4, 650Mhz to 1.4Ghz, 200/266 FSB, 1.7v to 1.75v, 256k L2

As the 1000MHz mark was approached and eventually reached, the deficiencies of the Athlon's off-chip L2 cache became clear, as the various versions were forced to slower and slower L2-to-internal clock ratios because of the slow speed of off-the-shelf SRAM. So, in June 2000, AMD released a new range of Athlons with 256k of full-speed L2 cache on-die, though attached by a 64-bit bus.

Palomino: Model 6, 1500+ to 2100+, 1.33Ghz to 1.73Ghz, 266 FSB, 1.75v, 256k L2

This is a significantly modified Thunderbird core intended at first for portable and workstation applications; it's designed for lower power consumption, supports SSE1 instructions, is equipped with hardware pre-fetch to improve performance on patterns of dynamically-predictable memory accesses, and in some models has multi-processor support. It also offers slightly higher clock speeds, at least in its later desktop incarnations, than the 0.18u Thunderbird.

Morgan: Model 7, Duron CPU, 900Mhz to 1.3Ghz, 200 FSB, 1.75v, 64k L2

A Palomino with 64k rather than 256k of full-speed L2 cache, and with the hardware pre-fetch disabled.

Thoroughbred A: Model 8, 1500+ to 2200+, 1.33Ghz to 1.8Ghz, 266 FSB, 1.5 to 1.65v, 256k L2, CPUID 680

These are 0.13u versions of the Palomino core. Thoroughbred A had significant performance problems, with 1850MHz or so its absolute upper limit.

Thoroughbred B: Model 8, 1700+ to 2800+, 2Ghz to 2.25Ghz, 266 to 333 FSB, 1.6 to 1.65v, 256k L2, CPUID 681

Thoroughbred B has a slightly different layout using two more metal layers, and upon its release was pushed to 2400MHz and more without exotic cooling. Some versions of Thoroughbred B released in late 2002 support a 166MHz DDR bus. The die size of the Thoroughbred B is bigger than the Thoroughbred A and is 9 layers, up from 8 layers in the Thoroughbred A core.

Barton: Model 10, 2500+ to 3200+, 1.83Ghz to 2.2Ghz, 333 to 400 FSB, 1.5 to 1.65v, 51k L2

This chip, announced at the start of February 2003 after a succession of delays, is a Thoroughbred B with a 166MHz DDR bus and 512K of level-2 cache.

Sledgehammer:

This is AMD's move into 64-bit computing, with a chip that supports the x86-64 architecture, a fairly straight extension of the x86 to 64-bit registers. The architecture is a noticably more advanced version of the K7, implemented in a 0.13u SOI (silicon on insulator) process; the initial version has a megabyte of L2 cache, occupying about two thirds of the die area. Like the Alpha EV7, Hammer has a memory controller on the chip itself; unlike the ten (eight for data and two for parity) Rambus channels on the Alpha EV7, the memory controller uses two channels of standard PC2700 DDR. This appears to be an extremely capable chip, with its fastest models very competitive with the fastest Xeons available at the time of release.

Photos from AMD CPU Chart